Publications by Lavanya Subramanian
2017
Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, Urbana-Champaign, IL, USA, June 2017
@inproceedings{abc, author = {Donghyuk Lee and Samira Manabi Khan and Lavanya Subramanian and Saugata Ghose and Rachata Ausavarungnirun and Gennady Pekhimenko and Vivek Seshadri and Onur Mutlu}, booktitle = {Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, Urbana-Champaign, IL, USA}, title = {Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms.}, url = {http://doi.acm.org/10.1145/3078505.3078533}, year = {2017} }
POMACS, January 2017
@article{abc, author = {Donghyuk Lee and Samira Manabi Khan and Lavanya Subramanian and Saugata Ghose and Rachata Ausavarungnirun and Gennady Pekhimenko and Vivek Seshadri and Onur Mutlu}, journal = {POMACS}, title = {Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms.}, url = {http://doi.acm.org/10.1145/3084464}, year = {2017} }
2016
TACO, January 2016
@inproceedings{abc, author = {Hiroyuki Usui and Lavanya Subramanian and Kevin Kai-Wei Chang and Onur Mutlu}, booktitle = {TACO}, title = {DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators.}, url = {http://doi.acm.org/10.1145/2847255}, year = {2016} }
CoRR, January 2016
@article{abc, author = {Donghyuk Lee and Yoongu Kim and Vivek Seshadri and Jamie Liu and Lavanya Subramanian and Onur Mutlu}, journal = {CoRR}, title = {Tiered-Latency DRAM (TL-DRAM).}, url = {http://arxiv.org/abs/1601.06903}, year = {2016} }
CoRR, January 2016
@inproceedings{abc, author = {Kevin Kai-Wei Chang and Gabriel H. Loh and Mithuna Thottethodi and Yasuko Eckert and Mike O{\textquoteright}Connor and Srilatha Manne and Lisa Hsu and Lavanya Subramanian and Onur Mutlu}, booktitle = {CoRR}, title = {Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism.}, url = {http://arxiv.org/abs/1602.00722}, year = {2016} }
IEEE Trans. Parallel Distrib. Syst., January 2016
@inproceedings{abc, author = {Lavanya Subramanian and Donghyuk Lee and Vivek Seshadri and Harsha Rastogi and Onur Mutlu}, booktitle = {IEEE Trans. Parallel Distrib. Syst.}, title = {BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling.}, url = {http://dx.doi.org/10.1109/TPDS.2016.2526003}, year = {2016} }
CoRR, January 2016
@article{abc, author = {Donghyuk Lee and Samira Manabi Khan and Lavanya Subramanian and Rachata Ausavarungnirun and Gennady Pekhimenko and Vivek Seshadri and Saugata Ghose and Onur Mutlu}, journal = {CoRR}, title = {Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips.}, url = {http://arxiv.org/abs/1610.09604}, year = {2016} }
2015
Proceedings of the 48th International Symposium on Microarchitecture, MICRO 2015, Waikiki, HI, USA, December 2015
@inproceedings{abc, author = {Lavanya Subramanian and Vivek Seshadri and Arnab Ghosh and Samira Manabi Khan and Onur Mutlu}, booktitle = {Proceedings of the 48th International Symposium on Microarchitecture, MICRO 2015, Waikiki, HI, USA}, title = {The application slowdown model: quantifying and controlling the impact of inter-application interference at shared caches and main memory.}, url = {http://doi.acm.org/10.1145/2830772.2830803}, year = {2015} }
2015 International Conference on Parallel Architecture and Compilation, PACT 2015, San Francisco, CA, USA, October 2015
@inproceedings{abc, author = {Donghyuk Lee and Lavanya Subramanian and Rachata Ausavarungnirun and Jongmoo Choi and Onur Mutlu}, booktitle = {2015 International Conference on Parallel Architecture and Compilation, PACT 2015, San Francisco, CA, USA}, title = {Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM.}, url = {http://dx.doi.org/10.1109/PACT.2015.51}, year = {2015} }
Proceedings of the 11th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, Istanbul, Turkey, March 2015
@inproceedings{abc, author = {Hui Wang and Canturk Isci and Lavanya Subramanian and Jongmoo Choi and Depei Qian and Onur Mutlu}, booktitle = {Proceedings of the 11th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, Istanbul, Turkey}, title = {A-DRM: Architecture-aware Distributed Resource Management of Virtualized Clusters.}, url = {http://doi.acm.org/10.1145/2731186.2731202}, year = {2015} }
CoRR, January 2015
@article{abc, author = {Lavanya Subramanian and Donghyuk Lee and Vivek Seshadri and Harsha Rastogi and Onur Mutlu}, journal = {CoRR}, title = {The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity.}, url = {http://arxiv.org/abs/1504.00390}, year = {2015} }
CoRR, January 2015
@article{abc, author = {Hiroyuki Usui and Lavanya Subramanian and Kevin Kai-Wei Chang and Onur Mutlu}, journal = {CoRR}, title = {SQUASH: Simple QoS-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators.}, url = {http://arxiv.org/abs/1505.07502}, year = {2015} }
2014
32nd IEEE International Conference on Computer Design, ICCD 2014, Seoul, South Korea, October 2014
@inproceedings{abc, author = {Lavanya Subramanian and Donghyuk Lee and Vivek Seshadri and Harsha Rastogi and Onur Mutlu}, booktitle = {32nd IEEE International Conference on Computer Design, ICCD 2014, Seoul, South Korea}, title = {The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost.}, url = {http://dx.doi.org/10.1109/ICCD.2014.6974655}, year = {2014} }
2013
19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 2013
@inproceedings{abc, author = {Donghyuk Lee and Yoongu Kim and Vivek Seshadri and Jamie Liu and Lavanya Subramanian and Onur Mutlu}, booktitle = {19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China}, title = {Tiered-latency DRAM: A low latency and low cost DRAM architecture.}, url = {http://dx.doi.org/10.1109/HPCA.2013.6522354}, year = {2013} }
19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 2013
@inproceedings{abc, author = {Lavanya Subramanian and Vivek Seshadri and Yoongu Kim and Ben Jaiyen and Onur Mutlu}, booktitle = {19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China}, title = {MISE: Providing performance predictability and improving fairness in shared main memory systems.}, url = {http://dx.doi.org/10.1109/HPCA.2013.6522356}, year = {2013} }
2012
39th International Symposium on Computer Architecture (ISCA 2012), Portland, OR, USA, June 2012
@inproceedings{abc, author = {Rachata Ausavarungnirun and Kevin Kai-Wei Chang and Lavanya Subramanian and Gabriel H. Loh and Onur Mutlu}, booktitle = {39th International Symposium on Computer Architecture (ISCA 2012)}, title = {Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems.}, url = {http://dx.doi.org/10.1109/ISCA.2012.6237036}, venue = {Portland, OR, USA}, year = {2012} }
2011
Reducing memory interference in multicore systems via application-aware memory channel partitioning.
44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, Porto Alegre, Brazil, December 2011@inproceedings{abc, author = {Sai Prashanth Muralidhara and Lavanya Subramanian and Onur Mutlu and Mahmut T. Kandemir and Thomas Moscibroda}, booktitle = {44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, Porto Alegre, Brazil}, title = {Reducing memory interference in multicore systems via application-aware memory channel partitioning.}, url = {http://doi.acm.org/10.1145/2155620.2155664}, year = {2011} }