Publications by Yoongu Kim
2016
CoRR, January 2016
@article{abc, author = {Yoongu Kim and Ross Daly and Jeremie Kim and Chris Fallin and Ji-Hye Lee and Donghyuk Lee and Chris Wilkerson and Konrad Lai and Onur Mutlu}, journal = {CoRR}, title = {RowHammer: Reliability Analysis and Security Implications.}, url = {http://arxiv.org/abs/1603.00747}, year = {2016} }
Computer Architecture Letters, January 2016
@inproceedings{abc, author = {Yoongu Kim and Weikun Yang and Onur Mutlu}, booktitle = {Computer Architecture Letters}, title = {Ramulator: A Fast and Extensible DRAM Simulator.}, url = {http://dx.doi.org/10.1109/LCA.2015.2414456}, year = {2016} }
CoRR, January 2016
@article{abc, author = {Kevin Kai-Wei Chang and Donghyuk Lee and Zeshan Chishti and Alaa R. Alameldeen and Chris Wilkerson and Yoongu Kim and Onur Mutlu}, journal = {CoRR}, title = {Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses.}, url = {http://arxiv.org/abs/1601.06352}, year = {2016} }
CoRR, January 2016
@article{abc, author = {Donghyuk Lee and Yoongu Kim and Vivek Seshadri and Jamie Liu and Lavanya Subramanian and Onur Mutlu}, journal = {CoRR}, title = {Tiered-Latency DRAM (TL-DRAM).}, url = {http://arxiv.org/abs/1601.06903}, year = {2016} }
CoRR, January 2016
@article{abc, author = {Donghyuk Lee and Yoongu Kim and Gennady Pekhimenko and Samira Manabi Khan and Vivek Seshadri and Kevin Kai-Wei Chang and Onur Mutlu}, journal = {CoRR}, title = {Adaptive-Latency DRAM (AL-DRAM).}, url = {http://arxiv.org/abs/1603.08454}, year = {2016} }
2015
21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015, Burlingame, CA, USA, February 2015
@inproceedings{abc, author = {Donghyuk Lee and Yoongu Kim and Gennady Pekhimenko and Samira Manabi Khan and Vivek Seshadri and Kevin Kai-Wei Chang and Onur Mutlu}, booktitle = {21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015, Burlingame, CA, USA}, title = {Adaptive-latency DRAM: Optimizing DRAM timing for the common-case.}, url = {http://dx.doi.org/10.1109/HPCA.2015.7056057}, year = {2015} }
2014
ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS '14, Austin, TX, June 2014
@inproceedings{abc, author = {Samira Manabi Khan and Donghyuk Lee and Yoongu Kim and Alaa R. Alameldeen and Chris Wilkerson and Onur Mutlu}, booktitle = {ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS {\textquoteright}14, Austin, TX}, title = {The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study.}, url = {http://doi.acm.org/10.1145/2591971.2592000}, year = {2014} }
ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014, Minneapolis, MN, USA, June 2014
@inproceedings{abc, author = {Yoongu Kim and Ross Daly and Jeremie Kim and Chris Fallin and Ji-Hye Lee and Donghyuk Lee and Chris Wilkerson and Konrad Lai and Onur Mutlu}, booktitle = {ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014, Minneapolis, MN, USA}, title = {Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors.}, url = {http://dx.doi.org/10.1109/ISCA.2014.6853210}, year = {2014} }
20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA, February 2014
@inproceedings{abc, author = {Kevin Kai-Wei Chang and Donghyuk Lee and Zeshan Chishti and Alaa R. Alameldeen and Chris Wilkerson and Yoongu Kim and Onur Mutlu}, booktitle = {20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA}, title = {Improving DRAM performance by parallelizing refreshes with accesses.}, url = {http://dx.doi.org/10.1109/HPCA.2014.6835946}, year = {2014} }
2013
The 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 2013
@inproceedings{abc, author = {Vivek Seshadri and Yoongu Kim and Chris Fallin and Donghyuk Lee and Rachata Ausavarungnirun and Gennady Pekhimenko and Yixin Luo and Onur Mutlu and Phillip B. Gibbons and Michael A. Kozuch and Todd C. Mowry}, booktitle = {The 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA}, title = {RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization.}, url = {http://doi.acm.org/10.1145/2540708.2540725}, year = {2013} }
The 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 2013
@inproceedings{abc, author = {Gennady Pekhimenko and Vivek Seshadri and Yoongu Kim and Hongyi Xin and Onur Mutlu and Phillip B. Gibbons and Michael A. Kozuch and Todd C. Mowry}, booktitle = {The 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA}, title = {Linearly compressed pages: a low-complexity, low-latency main memory compression framework.}, url = {http://doi.acm.org/10.1145/2540708.2540724}, year = {2013} }
The 40th Annual International Symposium on Computer Architecture, ISCA'13, Tel-Aviv, Israel, June 2013
@inproceedings{abc, author = {Jamie Liu and Ben Jaiyen and Yoongu Kim and Chris Wilkerson and Onur Mutlu}, booktitle = {The 40th Annual International Symposium on Computer Architecture, ISCA{\textquoteright}13, Tel-Aviv, Israel}, title = {An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms.}, url = {http://doi.acm.org/10.1145/2485922.2485928}, year = {2013} }
19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 2013
@inproceedings{abc, author = {Lavanya Subramanian and Vivek Seshadri and Yoongu Kim and Ben Jaiyen and Onur Mutlu}, booktitle = {19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China}, title = {MISE: Providing performance predictability and improving fairness in shared main memory systems.}, url = {http://dx.doi.org/10.1109/HPCA.2013.6522356}, year = {2013} }
19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 2013
@inproceedings{abc, author = {Donghyuk Lee and Yoongu Kim and Vivek Seshadri and Jamie Liu and Lavanya Subramanian and Onur Mutlu}, booktitle = {19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China}, title = {Tiered-latency DRAM: A low latency and low cost DRAM architecture.}, url = {http://dx.doi.org/10.1109/HPCA.2013.6522354}, year = {2013} }
2012
39th International Symposium on Computer Architecture (ISCA 2012), Portland, OR, USA, June 2012
@inproceedings{abc, author = {Yoongu Kim and Vivek Seshadri and Donghyuk Lee and Jamie Liu and Onur Mutlu}, booktitle = {39th International Symposium on Computer Architecture (ISCA 2012)}, title = {A case for exploiting subarray-level parallelism (SALP) in DRAM.}, url = {http://dx.doi.org/10.1109/ISCA.2012.6237032}, venue = {Portland, OR, USA}, year = {2012} }
2011
IEEE Micro, January 2011
@article{abc, author = {Yoongu Kim and Michael Papamichael and Onur Mutlu and Mor Harchol-Balter}, journal = {IEEE Micro}, title = {Thread Cluster Memory Scheduling.}, url = {http://dx.doi.org/10.1109/MM.2011.15}, year = {2011} }
2010
43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010, Atlanta, Georgia, USA, December 2010
@inproceedings{abc, author = {Yoongu Kim and Michael Papamichael and Onur Mutlu and Mor Harchol-Balter}, booktitle = {43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010}, title = {Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior.}, url = {http://dx.doi.org/10.1109/MICRO.2010.51}, venue = {Atlanta, Georgia, USA}, year = {2010} }
16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), Bangalore, India, January 2010
@inproceedings{abc, author = {Yoongu Kim and Dongsu Han and Onur Mutlu and Mor Harchol-Balter}, booktitle = {16th International Conference on High-Performance Computer Architecture (HPCA-16 2010)}, title = {ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers.}, url = {http://dx.doi.org/10.1109/HPCA.2010.5416658}, venue = {Bangalore, India}, year = {2010} }